Operation of Machine Language

Basic Operation of Machine Language

Read 3.1(P59-61), 3.3,3.5 4.1-4.4 in Ford & Topp

The control unit executes instructions from top to bottom. For each instruction it does the following:

FETCH instruction
- get ML instruction FROM MEMORY
- decode that instruction
EXECUTE instruction
- often read data FROM MEMOERY (sometimes data is part of instruction)
- perform operation (+, - etc.)
- often store data TO MEMORY

FETCH is the big time hog. Getting data from instruction is considered part of the FETCH and is especially slow. Storing data is also slow. A/L operations are quick.
The getting and storing of data is referred to as the "Von Neumann Bottleneck".

Basic Format Of ML instruction

in 68k - 16 bit OPCODE and 0 or more (usually 1 or 2) 16 bit extensions.
in SPARC (RISC) - everything is a 32 bit instruction.

Eg. ADDI.W #5,$A23FE8 ;add the constant 5 to memory location $A23FE8

somewhere in memory = $A034C0

A034C0 0679 Opcode
           2 0005 Extension
           4 00A2 Extension
           6 3FE8 Extension

Assuming 2 bytes are read/writen to memory each time, this instruction does 5 ML operations - 4 memory operations and one arithmetic operation. Costs 5 clock cycles. In RISC, 1 cycle per instruction always.

HARDWARE MODEL

Memory

Addresses are 24 bits in 68000, 32 bits (680x0) and 32 bits in SPARC.
Each BYTE=8 bits has its own address in both
Word = 16 bits, Longword (LONG) =32 bits in 68k
Halfword=16 bits, word= 32 bits doubleword=64 bits
Bit 0 is least significant (rightmost) bit. Bit 7/15/31 is most signifcant for various sizes

The 2/4/8 bytes of a thing are stored in consecutive memory locations.
Eg. ABCD1234 in address 500

BIG Endian	Little Endian
500 501 502 503	500 501 502 503
AB CD 12 34	34 12 CD AB
68K	80x86
SPARC	DEC ALPHA
IBM/370	DEC VAX
RS/6000
natural order?	00000005 stored at addr x in 4 bytes is 0005 stored at addr x in 2 bytes is 05 stored at addr x in 1 byte.

NOTATION

LSB of		34
MSB of	ABCD1234 is	AB
LSW of		1234
MSW of		ABCD

Boundary Alignment

Physical data path sizes between CPU and memory vary (8,16,32,64 are common) Consider a 16 bit data path. Memory can fetch only WORDs.
WORD at 0000, at 0002, at 0004 no problem.

If CPU needs BYTE at 0002 or 0003, the control unit can ignore lowest bits of word at 0002. OK
If CPU needs LONG word at 0002, it does 2 consecutive fetches. OK
If CPU needs WORD at 0003, then it fetches WORDs at 0002 and 0004 take them apart and reassemble them. BAD! It is slow or impossible.

SO a block of N bytes should be stored at a multiple of N.

68000- WORD/LONGWORD must be stored at even addresses. 680x0- no such restriction but very slow. SPARC- 2/4/8 must be 2/4/8 aligned. (instructions also). IBM/370- enforced 4/8 alignment.

In MAS use EVEN directive before any .W or .L storage allocation (or do .l them .w then .b . This is for people who like to shoot themselves in foot)

In SPARC .align 2/4/8