Conditional Branches

• Most CPUs contain a CC (Condition Code) register. Actually, it is a section of the SR or PSR register.
• The CC usually contains 4 bits: N Z V C
• The 680x0 also has an X bit, which we will not cover.
• The CC is set following every move or arithmetic instruction on the 680x0.
• Setting the condition code is optional on the SPARC. Add "cc" to the end of any arithmetic or logical opcode to set the condition code. (Use "addcc" instead of "add", for example.) Don't forget to do it when you need it!
• The Z bit is set to 1 if the result was Zero. (It is set if all bits of the result were 0's.)
• The N bit is set to 1 if the result was Negative. (In other words, it is set to the sign bit of the result.)
• The V bit is set to 1 if the operation caused an oVerflow (For add/sub, signed values are assumed). An overflow occurs when there is no encoding/representation for the correct answer in the space available.
• The C bit is set to 1 if the operation caused a carry (or borrow) out of the top bit. This is an overflow bit for unsigned values when using add/sub. (It has some other uses which may be covered later.)

Detection of overflow when adding or subtracting:

• The rule for addition is: There was an overflow if and only if the sign bit of the result is different from the signs of both operands. (Since adding two positive numbers cannot possibly give a negative result, and vice-versa, this makes sense.)
• Another trick that works: There is an overflow if and only if the carry coming in to the sign bit column is different from the carry coming out of the sign bit column (the C bit).
• For subtraction, use the same rules, but invert the sign of the second number.

For example, assuming the 8-bit addition Sum<-A+B, here is how the CC would be set:

 A  B   Sum   N Z V C
 -- -- -----  - - - -
 1F FF (1)1E  0 0 0 1
 01 FF (1)00  0 1 0 1
 40 40 (0)80  1 0 1 0
 A0 A0 (1)40  0 0 1 1
 00 01 (0)01  0 0 0 0

• Subtraction is done by twos complementing the second number, then adding. The CC is set as usual by this addition, except that the C bit is set to the opposite value when subtracting any number other than 0 (it becomes a "borrow bit" and not a "carry bit"). It still indicates an "unsigned overflow".
• For example, assuming the 8-bit subtraction Diff<-A­B, here is how the CC would be set:

 A  B  -B  Diff  N Z V C
 -- -- -- -----  - - - -
 1F FF 01 (0)20  0 0 0 1
 01 FF 01 (0)02  0 0 0 1
 FF 01 FF (1)FE  1 0 0 0
 22 00 00 (0)22  0 0 0 0
 40 40 C0 (1)00  0 1 0 0
 A0 60 A0 (1)40  0 0 1 0
 40 C0 40 (0)80  1 0 1 1

• Compare instructions exist on most machines, and their sole purpose is to set the CC. They behave exactly the same as a subtraction, except that the result is discarded.
• For 68000, use "cmp" (same rules as for add/sub).
• For SPARC, use a "subcc" with %g0 for the result. There is no separate compare instruction. (RISC)
• Following a comparison, there is usually a conditional branch instruction which will branch to some address (label) if the CC bits satisfy a certain condition. The syntax for both SPARC and 680x0 is:

 bcc Label (replace "bcc" by one of the opcodes below)

• There are four types of conditional branches:
  • Those that check one particular bit in the CC
  • Those that are used following comparisons of signed integers
  • Those that are used following comparisons of unsigned integers
• There are also the unconditional branches - branch always and branch never

Branch condition	Branch if	680x0 opcode	SPARC opcode
Check on particular bit in the CC:
Z bit is 1	Z=1	beq	be
Z bit is 0	Z=0	bne	bne
N bit is 1	N=1	bmi	bneg
N bit is 0	N=0	bpl	bpos
V bit is 1	V=1	bvs	bvs
V bit is 0	V=0	bvc	bvc
C bit is 1	C=1	bcs	bcs
C bit is 0	C=0	bcc	bcc
Use after SIGNED comparisons (eg. CMP A,B or SUBCC B,A,%g0)
B = A	Z = 1	beq	be
B < > A	Z = 0	bne	bne
B < A	N * V = 1	blt	bl
B >= A	N * V = 0	bge	bge
B <= A	Z + (N * V) = 1	ble	ble
B > A	Z + (N * V) = 0	bgt	bg
Use after UNSIGNED comparisons (eg. CMP A,B or SUBCC B,A,%g0)
B = A	Z = 1	beq	be
B < > A	Z = 0	bne	bne
B < A	C = 1	blo (bcs)	blu (bcs)
B >= A	C = 0	bhs (bcc)	bgeu (bcc)
B <= A	Z + C = 1	bls	bleu
B > A	Z + C = 0	bhi	bgu
Unconditional branches
Always branch	1 = 1	bra	ba
Never branch	1 = 0	---	bn

WARNING - SPARC uses "delayed branching"